Design-Reuse

A Digital Design Flow for Differential ECL High Speed Applications

This paper presents a digital design flow in order to design high performance differential Emitter Coupled Logic (ECL) circuits efficiently. The proposed flow is similar to the ordinary digital CMOS ...
EDN

Emitter Coupled Logic Signaling

The PECL (Positive ECL) IO standard is simpler to design with when compared with ECL because it referenced to +5V which is a common voltage supply. PECL has the same 800 mV swing as ECL. LVPECL is ...
EDN

Save valuable picoseconds using ECL-wired OR

Often, when you are designing with high-speed ECL (emitter-coupled logic), you have too little time between clock cycles to implement logic functions using gates between flip‑flops. In these cases, ...
Electronic Design

Ultra-High Speed Logic Devices Housed In Mini-SOP Packages

Three new ultra-high speed logic devices have been added to the company's ECL Pro logic family—the ever-expanding ECL Pro logic family is said to offer an easy upgrade path from On Semiconductor's ...
Electronic Design

Translator Family Creates ECL-To-LVDS Bridges

The companyÕs line of timing and logic products now includes a family of translators for use in bridging devices with ECL I/O to LVDS I/O used in todayÕs CMOS ICs. Supporting OC-3 to OC-192 systems, ...
Design-Reuse

Phase-frequency detector in ECL logic

The phase-frequency detector (PFD) consists of 2 D-trigger with reset from external circuit, performed in ECL logic and multiplexer, which allow to sw ...
Hackaday

emitter-coupled logic

One of the best parts about Hackaday is how much you learn from the projects that people tackle, especially when they are repairs on old gear with unknown failure modes and potentially multiple ...